1. Field of the Invention
The present invention relates to a parallel operation system in which a plurality of AC output inverters are operated in parallel with respect to a common load.
2. Related Background Art
In the case where two AC power supply devices (hereinafter simply referred to as power supplies) 1, 2 are, as illustrated in FIG. 32, operated in parallel with respect to a common load 4. Let E.sub.1, E.sub.2 be the output voltages of the respective power supplies 1, 2; let Z be the internal impedances, equal to each other, of the respective power supplies 1, 2; and let I.sub.1, I.sub.2 be the output currents of the power supplies 1, 2. It is also assumed that E.sub.A is the voltage (common output voltage) at a common connecting point A to which the load 4 is connected; R is the resistance component of an internal impedance Z; and X is the reactance. This internal impedance Z can be expressed by the following formula: EQU Z=R+jX (1)
In this case, an absolute value .vertline.Z.vertline. of the internal impedance and an internal impedance angle 0 are given by the following formulae: ##EQU1## Further, in a circuit illustrated in FIG. 34, the following formula is established: EQU E.sub.1 -ZI.sub.1 =E.sub.2 -ZI.sub.2 =E.sub.A ( 4)
If a cross current is defined as a difference between a self-output-current and an average of individual output currents, a cross current .DELTA.I.sub.1 seen from the power supply 1 and a cross current .DELTA.I.sub.2 seen from the power supply 2 are expressed by the following formulae: EQU .DELTA.I.sub.1 =I.sub.1 -1/2(I.sub.1 +I.sub.2)=1/2(I.sub.1 -I.sub.2)(5) EQU .DELTA.I.sub.2 =I.sub.2 -1/2(I.sub.1 +I.sub.2)=1/2(I.sub.1 -I.sub.2)(6)
From the formula (4), the following formula is established: EQU E.sub.1 -E.sub.2 =Z(I.sub.1 -I.sub.2) (7)
From the formulae (5), (6) and (7), the following formula is established: EQU .DELTA.I.sub.1 =-.DELTA.I.sub.2 =1/2(E.sub.1 -E.sub.2)/Z (8)
From the formula (8), it can be understood that phases of the cross currents .DELTA.I.sub.1, .DELTA.I.sub.2 are delayed by an internal impedance angle .phi. with respect to differential voltages E.sub.1-E.sub.2, E.sub.2 -E.sub.1.
Besides, from the formula (4), the following formula is established: EQU E.sub.A =1/2(E.sub.1 +E.sub.2)-Z(I.sub.1 +I.sub.2) (9)
In general, the internal impedance is much smaller than a load impedance, and in this case, the formula (9) is expressed as follows: EQU E.sub.A =1/2(E.sub.1 +E.sub.2) (10)
Now, supposing that the output voltages E.sub.1, E.sub.2 of the power supplies 1, 2 are in the equiphase; and the absolute values are different by .DELTA.E (i.e., .vertline.E.sub.1 .vertline.-.vertline.E.sub.2 .vertline.=.DELTA.E), a relation of vector on the basis of the output voltage E.sub.1 is shown in FIG. 33. To be specific, the cross current vector I.sub.1 is delayed by the internal impedance angle .phi. with respect to the differential voltage vector (E.sub.1 -E.sub.2). A common output voltage vector E.sub.A is substantially in the equiphase to the output voltage vectors E.sub.1, E.sub.2 of the two power supplies. Hence, in such a case that the phases are identical; whereas the absolute values are different, the cross current vector .DELTA.I.sub.1 is directed in parallel to (vertical to a virtual vector E.sub.AY vertical to a virtual vector E.sub.AX) a direction of a virtual vector E.sub.AX which is more delayed by the internal impedance angle .phi. than a common output voltage vector EA.
Next, it is assumed that the absolute values of the output voltages E.sub.1, E.sub.2 of the power supplies 1, 2 are identical, whereas the phases are different by .theta.. A relation of vector on the basis of the output voltage E.sub.1 is shown in FIG. 34. In this case, the differential voltage vector (E.sub.1 -E.sub.2) is delayed by (90.degree.-1/2.theta.) with respect to the output voltage vector E.sub.1 of the power supply 1. The cross current vector I.sub.1 is delayed by the internal impedance angle .phi. with respect to the differential voltage vector (E.sub.1 -E.sub.2). The common output voltage vector E.sub.A advances substantially through 1/2.theta. with respect to the output voltage vector E.sub.1 but is delayed substantially by 1/2.theta. with respect to the output voltage vector E.sub.2. Hence, in such a case that the absolute values are identical; whereas the phases are different, the direction of the cross current vector I.sub.1 is vertical (parallel to the virtual vector E.sub.AY vertical to the virtual vector E.sub.AX) to the direction of the virtual vector E.sub.AX which is more delayed by the internal impedance angle .phi. than the common output voltage vector E.sub.A.
Detected, as can be comprehended from the contemplation about the two vector diagrams given above, are a component I.sub.1x parallel (vertical to E.sub.AY) to the reference vector E.sub.AX of the cross current vector I.sub.1 and a vertical component .DELTA.I.sub.1Y (parallel to E.sub.AY) on the basis of the virtual vector E.sub.AX (or virtual vector E.sub.AY vertical thereto) which is more delayed by the internal impedance angle .phi. than the common output voltage E.sub.A. It is possible to eliminate an output voltage absolute value deviation between the mutual power supplies by performing the output voltage absolute value control so that the parallel component .DELTA.I.sub.1X becomes zero. Further, it is also feasible to eliminate an output voltage phase deviation between the power supplies by effecting the output voltage phase control of the power supplies so that the vertical component .DELTA.I.sub.1Y becomes zero.
FIG. 35 is a block diagram illustrating a conventional parallel operation system of AC output inverters. A first inverter device 1 supplies the electric power to a load 4 while performing the parallel operation via an output bus 3 with respect to a second inverter device 2 having the same construction. The first inverter device 1 includes main components such as an inverter body 140, a reactor 141 constituting a filter and a condenser 142. The first inverter device 1 converts the electric power of a DC power supply 5 into an alternate current and is connected via an output switch 143 to an output bus 3.
A voltage control circuit 146 controls an internally generated voltage by executing a pulse width modulation of the inverter body 140 through a PWM circuit 145 on the basis of signals of a voltage setting circuit 147 and a voltage detection circuit 148.
A detection signal I1a is obtained from an output current I.sub.1 of the first inverter device by means of a current detector 144. Obtained by a cross current detection circuit 151 is a difference between the former detection signal and a detection signal I2a similarly obtained from the second inverter device 2, i.e., a signal I.sub.1 corresponding to the cross current. Formed next from a phase shifter 150 are a voltage E.sub.AX which is more delayed by the internal impedance angle .phi. and a voltage E.sub.AY which more advances by 0.degree.-.phi. than the common output voltage E.sub.A. An arithmetic circuit 152 outputs a signal .DELTA.Q proportional to the component .DELTA.I.sub.1X parallel to E.sub.AX of the cross current .DELTA.I.sub.1. An arithmetic circuit 153 outputs a signal P proportional to the component .DELTA.I.sub.1Y parallel to E.sub.AY of the cross current .DELTA.I.sub.1.
The signal .DELTA.Q proportional to the component .DELTA.I.sub.1X is given as an additional target value to the voltage control circuit 146. The internally generated voltage of the inverter body 140 is adjusted several % or thereabouts at the maximum so that .DELTA.Q becomes 0. The output voltage absolute values of the two inverters thereby become identical.
On the other hand, the signal proportional to .DELTA.I.sub.1Y is inputted via an amplifier 154 constituting a PLL circuit to a reference oscillator 155. A frequency of the reference oscillator 155 is infinitesimally adjusted so that .DELTA.P becomes 0, thus controlling a phase of the internally generated voltage of the inverter body 140. The output voltage phases of the two inverters are made coincident.
In this manner, the absolute values and phases of the voltages are controlled so that both of .DELTA.Q and .DELTA.P become zero, as a result of which the cross current between the two inverters is eliminated. The load is stably shared.
The conventional parallel operation system of the inverters, which has been constructed in the way described above, therefore presents the following four problems. The first problem is that the phase of the internally generated voltage of the inverter and the mean value of the voltages are controlled to balance the shared currents, and it is therefore difficult to improve a control response speed. In particular, the instantaneous cross current can not be controlled. The second problem is that the cross current control can not be effected a high speed because of requiring a filter when detecting the cross current while separating the cross current into an active component and a reactive component. For this reason, there is a limit in terms of application in a high-speed voltage control system of instantaneous waveform control for keeping the output of the inverter in a high quality sine wave with a less amount of distortion. The third problem is that the control circuit becomes intricate because of controlling the cross current while separating the cross current into the active and reactive components. The fourth problems is that it is difficult to perform the parallel operation of the inverters and other power supply. Especially, even when operating the inverters and the power system in parallel, it is hard to control the cross current.